Selected work
GPU · SystemsC++ · CUDA · TensorRT
Silky
60fps in, 240fps out — never leaving the GPU
A zero-copy video frame-interpolation pipeline: hardware decode, a TensorRT-optimized RIFE network, and hardware encode — with frames that never leave VRAM.
Role — Solo GPU / systems engineer
- C++
- CUDA
- TensorRT
- NVDEC / NVENC
- ONNX
Silky decodes with NVDEC, runs RIFE optical-flow interpolation through TensorRT, and re-encodes with NVENC, keeping every frame on the GPU end to end. I wrote the pipeline orchestration, the NVRTC-compiled colour-space kernels, and the interpolator interface around the third-party model and NVIDIA libraries.
It targets 120, 144, or 240fps from 60fps source, in FP16 or FP32, encoding to H.264 or HEVC.
What's notable
- Zero host round-trips — NVDEC → TensorRT → NVENC entirely in VRAM
- NVRTC-compiled CUDA colour-space kernels
- FP16 / FP32 precision, H.264 / HEVC output
- 60 → 120 / 144 / 240fps targets